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The PC203 provides the processing power needed by demanding applications such as WiMAX and WiBRO, and carrier-class wireless infrastructure.
Its three inter picoArray interconnect (IPI) buses allow the implementation of powerful multi-chip signal processing systems, giving designers an extendible hardware platform on which to base a range of products.
The PC203 is available in two versions: the standard variant has a 248-element picoArray, while the enhanced (-10) version has 273 picoArray processors in total. The extra processing power of the -10 version allows engineers to implement higher functionality in their designs, and produces significant savings in device count in multi-chip systems.
Both the standard and -10 variants include fast flexible hardware acceleration of common signal processing tasks such as FFT/IFFT, Convolution Turbo Codes, Viterbi, and Reed-Solomon. An on-chip AES/DES/3DES encryption block speeds security processing.
The performance of a single PC203 device at 160MHz is summarized below:
|Operation||Peak / sec. / device (PC203 @ 160MHz)|
|Turbo Code (8 iterations)||18||18||Mbit/s|
An SDRAM interface provides a direct connection to DDR-II SDRAM for off-chip buffering needs. It facilitates a 16- or 32-bit data bus capability to balance performance and economics. A high performance processor interface bus allows direct connection to Wintegra Winpath or Freescale PowerQUICC processors for basestation-scale MAC solutions.